Core architecture

Veronte Autopilot 1x is equipped with a Dual-Core Microcontroller. Both cores, hereinafter called Core 1 (C1) and Core 2 (C2), work together to perform information processing operations efficienty and to coordinate the activities of other system components.

It is crucial to understand the performance of C1 and C2 in order to properly handle Autopilot 1x tasks.

  • Core 1: It presents the following operation threads.

    • High: 1kHz guaranteed. Hardware interrupt in charge of certain critical or high-priority tasks which must be executed with a constant and predictable frequency.

      Note

      There is a permitted frequency fluctuation of 1%.

    • Low: Not guaranteed rate. In charge of non-priority tasks which tolerate non-guaranteed time consistency.

  • Core 2: Execution rate of 400 Hz (configurable from 1x PDI Builder application).

Task distribution

Tasks distribution between processors:

Core 1

Core 2

High

Low

  • Guidance, Navigation and Control (GNC)

  • Mission updating

  • Automations management

  • RAM writing

  • Sensors reading

  • FTS Management

  • I/O management (data from peripherals to internal pre-processing queues)

  • Telemetry and logs management

  • Communicaction management

  • Files management

  • Additional helper tasks

  • SD writing

A proper comprehension of how cores manage different tasks, considering the priorities and execution rates previously explained, may be valuable to avoid delays in data processing and achieving a balanced functioning of the Veronte system.

Aspects to be considered:

  • C1 and C2 information interchange: Cores share information through the Cross-Core queue, hence overfilling this queue may result in late processing of data.

  • Tasks distribution between C1 threads: If acquisition tasks take too much processing time, C1 low task may not be executed as expected.

  • C1 High interruptions: C1 high may interrupt C1 low task execution. In this case, C1 low will continue its execution at the same point once high priority tasks are fullfilled.

Monitoring variables

Distributing resources is decisive for the proper functioning of the system. For that reason, core-related values are monitored.

Note

For further information regarding these variables, please consult their IDs in the Lists of Variables section of the present manual.

C1 is monitored by the following variables:

Core 1

High

Low

  • Acquisition Step Missed (BIT 402)

  • CIO Hi Overload warning (BIT 403)

  • Acquisition Task Timestep (RVar 2047)

  • Acquisition Task Maximum Timestep (RVar 2048)

  • Acquisition Task Average CPU Ratio (RVar 2050)

  • Acquisition Task Maximum CPU Ratio (RVar 2051)

  • Acquisition Task Average Time (RVar 2052)

  • Acquisition Task Maximum Time (RVar 2053)

  • Identifier of max duration step in acquisition (UVar 399)

C2 is monitored by the following variables:

Core 2

Cross-Core queue is monitored by the following variables:

Cross-Core queue

  • Cross Core Message Queue CPU Ratio (RVar 2049)

  • Cross-Core Message Queue Usage (RVar 2056)